As part of our goal to be a full ASIC services company Aizyc has put together a team of strong Physical Design engineers with proven experience in sub-micron ASIC designs. The team helps our customers to ease their design bottleneck thereby achieving the final design closure on time, with exhaustive experience of working on multi-million gate ASIC/SoC design projects. The team has several first-time silicon success tape outs to its credit.

Services include custom layout of IOs and Analog macros, layout creation for leaf cells and top level integration, layout verification through LVS, DRC & DFM checks, RV/IR/EM fixes, reliability checks and executing Engineering Change Orders (ECO). Our team is proficient at LVS/DRC debug, custom design tools like Cadence Virtuoso, DFM/RV/IR/EM concepts and scripting skills.

Service Offerings

• Physical synthesis and Floor planning
• DRC and LVS to check integrity of the design
• Clock skew management and signal integrity issues
• Timing closure and post-layout simulation
• Verifying sub-nano physical design issues
• Tools Experience: Magma, Cadence, Synopsys

Synthesis

Development of synthesis scripts to target the design onto a specific ASIC technology.

DFT / ATPG

Expertise in developing a complete test strategy for your ASIC design to deliver high fault coverage. This includes

• Scan / ATPG

• RAMBIST

• Testing of embedded IP

• JTAG

STA / Timing Closure

We can develop complete timing constraints to support timing driven place & route tools and full Static Timing Analysis on the post-layout netlist, to confirm that the design meets the required performance targets prior to tapeout. We are skilled at working closely with the layout team to achieve efficient timing closure on technologies down to 65nm.

Formal verification

Formal verificationto confirm logical equivalence between RTL and the synthesised netlist and then gate-gate checking on any subsequent versions of the design as it goes through the design flow ( DFT, physical optimisation etc)