Aizyc SD/SDIO 3.0 Host IP provides supports for various system interfaces – VCI, AHB, APB  and OCP. Number of slots[1/2] available is also configurable. It provides UHS-I modes of operation - DS, HS, SDR12, SDR25, SDR50,SDR104 and DDR50. This IP also provides optional support for eMMC 4.41 card interface. The IP core is portable to either an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform. For more information please browse the IP description from the SoC IP Cores menu above.

Aizyc PCIe to SD 3.0 Host evaluation platform is used to facilitate the development and evaluation of SD3.0 Host/Device IPs implemented in Xilinx Spartan 6 FPGA. This board is designed in a 4-layer with timing goals to meet the SD specification and 3.0 performance. SI analysis has also been performed on this design.This FPGA board plugs into a PCIe slot. This gives the flexibility to interface the FPGA to PCIe bus. The FPGA device used is XC6SLX100-3For SD 3.0 Host, the application supported is PCIe to SD 3.0 Host Controller Card.