Aizyc Serial Low-power Inter-chip Media Bus (SLIMbus™) Device Controller IP core provides complete implementation for standard interface between baseband or application processor and peripheral components in mobile terminals, as per MIPI® SLIMbus™ specification version 1.01.01.

Aizyc SLIMBus™ Device Controller IP provides robust, scalable, synchronous, 2-wire, configurable, Time Division Multiplexed, low-power, high-speed, and cost-effectivesolution with applications in digital audio and control solutions. Along with the mobile terminals, this IP core has equally well applicable application in other moderate data rate devices like audio systems, speakers, media players, microphone and ringers.

Aizyc SLIMbus™ Device IP core effectively replaces many other digital legacy audio buses such as PCM and I2S, as well as control buses such as I2C, SPI or UART by providing flexible and dynamic assignment of bus bandwidth between digital audio and non-audio control and data functions.

It is designed for a throughput of up to 28.8 Mbps and capable of supporting multiple devices on the system.

The IP core is portable to either an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform. A complete test environment with constraint randomized test cases is provided with IP core. Aizyc provides full support to help in complete integration.