Aizyc HDCP  (High-bandwidth Digital Content Protection ) IP Core is a hardware and software based Digital Rights Management (DRM) solution for next generation multimedia SoCs.

Overview

The HDCP IP Core offers out of the box solution for SoC designers to integrate itself with minimal tweaking. The IP comes with supporting firmware in µC/OS-II, ThreadX and Linux. The HDCP2.0 IP core has both Tx and Rx and is highly configurable.

Authentication: A HDCP transmitter and receiver pair performs authentication before it does AV data transfer. Authentication involves a series of control messages to be exchanged among transmitter and receiver. As two things are established (1) receiver is authentic (2) a secret key that will be used for encrypting AV data.

Hardware and Software together play a role in authentication process. Software detects receiver when it is connected and directs the HW to start authentication. HW generates control messages and associated data for authentication, writes the data to registers and interrupts SW to let it transfer messages to Receiver. Control messages received from the other end are written to register set by SW thereby HW reads and performs authentication checks.

Feature List

• Compliant to HDCP Rev 2.0
• Performs Authentication and Session management
• Performs  encryption and decryption
• Supports repeaters.
• Supports 32-bit APB slave interface for register configuration.
• Linux based software is provided.
• AES-128 in CTR mode
• SHA-256 in HMAC mode
• Random Number Generator compliant to NIST-SP 800 90
• Gate count - 120K
• Platforms- ThreadX, Linux, Ucos-ii RTOs

Functional Block Description

HMAC_SHAHMAC

(Hash-based Message Authentication Code)  block is a specific construction for calculating a message authentication code (MAC) involving a cryptographic hash function in combination with a secret key.SHA-2 is used in HMAC mode.

In HDCP authentication HMAC is used in three of the processes.

(1)     to compute H/H’ using Kd,

(2)     to compute V and V’ for authentication with devices connected across repeaters and

(3)     to compute L/L’ for locality check.

Tx/Rx registers

Registers are used for HW/SW interface. SW accesses registers over APB interface. HW uses registers to set the message and data for control messages and raises and interrupt to SW to let it transfer the message to receiver. The messages received at system are written to receive set of registers and flagged using control bits to let the HW process them.

AES

128-bit AES is used in CTR Mode. AES is used in authentication for RNG, master key generation, key derivation and also in data transfer

RNG

Deterministic Random Number Generator used in both HDCP Transmitter and HDCP Receiver. Counter based DRBG using AES-128 Block cipher specified in NIST SP 800-90 is used. It generates random values for secret key material rtx, rrx, riv, rn, km, ks.

Software Operations

MASTERKEY encryption: Master key encryption is done using RSHES-OAEP encryption scheme defined by PKCS #1V.2.1 RSA cryptography standard.

MASTERKEY decryption: Master key decryption is done using RSHES-OAEP encryption scheme defined by PKCS #1V.2.1 RSA cryptography standard.

SRM and signature verification: Receiver certificate’s signature and SRM are verified using RSASSA-PKCS1-V1.5 scheme as defined in PKCS#1 V.2.1 RSA cryptography standard.

Clocks and Resets

HDCP2.0 works on a single clock, clk. Clock frequency is not governed by HDCP specification. Based on implementation we expect to achieve 135 MHz.