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Aizyc Serial Low-power Inter-chip Media Bus (SLIMbus™) Device Controller IP core provides complete implementation for standard interface between baseband or application processor and peripheral components in mobile terminals, as per MIPI® SLIMbus™ specification version 1.01.01.

Overview

Aizyc SLIMBus™ Device Controller IP provides robust, scalable, synchronous, 2-wire, configurable, Time Division Multiplexed, low-power, high-speed, and cost-effectivesolution  with applications in digital audio and control solutions. Along with the mobile terminals, this IP core has equally well applicable application in other moderate data rate devices like audio systems, speakers, media players, microphone and ringers.

Aizyc SLIMbus™ Device IP core effectively replaces many other digital  legacy audio buses such as PCM and I2S, as well as control buses such as I2C, SPI or UART by providing flexible and dynamic assignment of bus bandwidth between digital audio and non-audio control and data functions. It is designed for a throughput of up to 28.8 Mbps and capable of supporting multiple devices on the system.

The IP core is portable to either  an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform. A complete test environment with constraint randomized test cases is provided with IP core.  Aizyc provides full support to help in complete integration.

Feature List

  • Compliant to MIPI® SLIMbus™ specifications version 1.01.01

  • Supports one or more generic devices

  • Each generic device supports 1 to 64 programmable input/output ports

  • Maximum throughput supported 28.8 Mbps

  • Support multiple concurrent sample rates on single bus

  • Support all data transports protocols

  • Support reconfigurable data organization and data rates

  • Clock recovery mechanism

  • Supports all core messages

Functional Block Description

Physical Layer

The Physical Layer provides for the transmission and reception of the

SLIMbus™ bit stream between Components.  The two lines, CLK and  DATA, are the only wires required to implement the bus. The CLK line distributes a high-quality, unidirectional clock signal to all Components. The DATA line is bidirectional, carrying all information sent or received on the bus. Information is signalled using Non-Return-to-Zero Inverted, or NRZI encoding

Frame Layer

The SLIMbus™ Frame Structure interleaves Control Space channels and Data Channels into a single, serialized bit stream. Each Component uses a functional block called the Frame Layer to combine control and data information into a single bit stream for transmission on the bus. Also, the Frame Layer is used to split the incoming bit stream into separate control and data streams. In addition, a Framer also contains logic to generate the Guide and Framing Channels used to synchronizeDevices on the bus.

Interface Device

An Interface Device provides bus management services for the component in which it resides. The Interface Device monitors the Frame Layer and Message Protocols implemented by the Component. Interface Device also manages Component Reset so that component can properly sequence its Devices. In addition, the Interface Device reports information about the status of the component.

Generic Device

The Generic Device provides basic SLIMbus™ functionality for a device. It provide single or multiple interfaces to external applications. The generic device supports all transport protocols including isochronous and extended asynchronous transfers.

Parallel Interface

The generic device provides parallel interface to the applications connected to SLIMbus™ device. Other interface such as I2S, SPI, I2C, UART or custom interfacescan also be implemented.

Host Interface

The device IP provides AHB interface to the host to control the operation of SLIMbus™ device IP.

 

Deliverables

IP Downloads

Please email us at sales@aizyc.com or visit our Downloads page

IP Deliverables

  1. Verilog source / encrypted code of the IP core
  2. Verilog Test environment  and test scripts
  3. Synthesis constraints and scripts
  4. Documentation – Design , Verification & Integration guide
  5. FPGA validation platform (Xilinx / Altera)

Pricing

IP Licensing

Our Pricing varies based on your Needs.
1. Per product, multiple products or perpetual
2. With and without source code
3. Default email support for all IPs is 12 months
Shoot us an email with your requirement sales@aizyc.com