Clients Talk

We were sceptical intially to try a new vendor but Aizyc’s professionalism and “Customer is King” attitude has spoiled us with new levels of expectations in the offloaded environment.
-Cypress-

Request For Quotation
Case Studies & White Papers
Contact Us

 

Aizyc  I2C Controller IP is compact low power and scalable IP core. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring communication over short distance between many devices.

Overview

The standard VCI interface provided in I2C IP core makes  integration easy into any design.I2C controller IP core is fully synthesizable core suitable for different process. The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases  and our full support during integration.

Feature List

  • Compliant to version 2.1 of the I2C Bus standardI2C IP Core
  • System Bus Interface - VCI
  • Optional Bus Interface - AHB, APB, OCP
  • Data transfers up to 400 Kbps
  • Supports Master Transmitter Mode - Serial data output on SDA and clock on SCL output
  • Supports Master Receiver Mode - Serial data is received via SDA while SCL outputs the serial clock
  • Single master mode
  • Supports up to eight slave devices with unique address
Functional Block Description

Host Interface
The host interface is a 32 bit VCI slave interface. This interface is used to integrate the IP core within the SoC design and to read/ write the internal registers of the core.

Control and Status Registers
This block consists of I2C registers for data transfer and control and status information. These registers are programmable through VCI interface.

Clock Generator
This functional block controls the generation of I2C clock from the IP core for data transfer.

Command Control
This block consists of state machines for sending command and data bytes on to the I2C bus.

Transmit and Receive
This block has the buffers and the control logic for transmitting and receiving the data through host and I2C interfaces.
 

Deliverables

IP Downloads

Please email us at sales@aizyc.com or visit our Downloads page

IP Deliverables

  1. Verilog source / encrypted code of the IP core
  2. Verilog Test environment  and test scripts
  3. Synthesis constraints and scripts
  4. Documentation – Design , Verification & Integration guide
  5. FPGA validation platform (Xilinx / Altera)