Aizyc NAND Flash Controller IP is compact, low power and highly configurable IP complaint to latest ONFI standard revision 2.2. It supports both high capacity Multi-level Cell (MLC) and Single S Level Cell (SLC). It is designed to support NAND Flash memory devices from all leading providers Samsung, Toshiba, Micron, ST-Micro and others.
The IP has configurable RAM size to best suit your needs. Features like programmable flash interface timings adds to the flexibility of the IP. The IP implements AHB master/slave to interface with the host processor. It also provides optional system interface - APB, AXI, OCP, VCI. BCH-Error Correction Code is implemented in the design to support up to 32 bits error detection and correction mechanism.
Small foot print and high configurability has made Aizyc NAND Flash controller IP best suited for applications in Consumer Electronics Products like cell phones, memory drives, PDAs, Digital cameras, Digital TVs, Gaming consoles and others. The IP core is portable to either an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform. A complete test environment with constraint randomized test cases is provided with IP core. Aizyc provides full support to help in complete integration
Functional Block Description
NAND Flash Interface
This block directly interfaces with the external NAND flash device and generates command, address and data cycles on the flash interface. The flash controller block supports both asynchronous and synchronous flash interfaces.
The AHB master/slave interface is used to program internal control registers, read the status registers and transfer data from the flash device. The host processor uses this interface to control the function of NAND flash controller.
Control and Status Registers
The configuration and operation of the NAND Flash Controller is controlled by host processor through the Control and Status registers. Configuration includes the setting of hold time, setup time, wait state, memory configuration, timing modes, etc. The Status Registers also provide operating status of the flash interface such as Busy and Data Ready signals.
- Verilog source / encrypted code of the IP core
- Verilog Test environment and test scripts
- Synthesis constraints and scripts
- Documentation – Design , Verification & Integration guide
- FPGA validation platform (Xilinx / Altera)
Our Pricing varies based on your Needs.
1. Per product, multiple products or perpetual
2. With and without source code
3. Default email support for all IPs is 12 months
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