Aizyc SDIO (Secure Digital I/O) Device Controller IP Core is compact low power and scalable IP core. Flexible architecture of the core will support wide range of applications – GPS , UWB, WiMAX, Bluetooth, 802.11n etc. The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.

Overview

It has fixed internal register map. The fixed area will contain information about the card and some mandatory and optional registers. The CIS and CSA will be implemented in internal memory of CPU subsystem. The SDIO registers (CCCR and FBR) can be programmed both by SD host (through SD bus) and CPU (through OCP interface).AHB Master & Slave interface in SDIO IP will allow easy integration in to SOC. Flexible architecture of the core will support wide range of applications – GPS , UWB, WiMAX etc.

Feature List

• SDIO card specification version 2.00
• SD specification version 2.00
• Supports SPI, SD1 and SD4 modes 1-bit SD and 4-bit SD transfer modes
• Clock range 0-25MHz for full Speed card 0-50 MHz for high speed IO card
• SDIO features : Suspend/Resume, Interrupt, Read Wait
• Supports all SDIO commands including IO52 and IO53
• Programmable register through AHB interface System
• Bus Interface – AHB
• Optional Bus Interface - OCP, VCI, APB, AXI
• Multi-block read and write CRC7 and CRC16 checksum logic

Functional Block Description

SDIO Registers

The registers block consists of fixed internal registers called Common IO Area (CIA). The registers within CIA are provided to enable/disable and control operation of IO functions. There are three types ofregisters supported within CIA .

• Card Common Control Registers (CCCR)
• Function Basic Registers (FBR)
• Card Information Structure (CIS)

AHB  DMA

The 32-bits AHB master interface is used to access the function specific registers and the memory. It supports following transactions

• Simple Read
• Simple Write
• Burst Read (INCR and STRM)
• Burst Write (INCR and STRM)

Bus Interface Unit

The SDIO bus interface unit block communicates to the SD host through SD bus. This block contains CRC7 and CRC 16 generator and checker logic for CMD and DAT lines respectively.

CMD/RESP State Machine

It controls the Command receive and Response transmit timing in SDand SPI mode of operations.

Interrupt State Machine

This state machine implements the interrupt timing control as per SDIO 2.0 specifications. It supports optional Interrupt period at the Data Block gap in 4-bit SD mode. It also implements the Read Wait Control logic.

Suspend/Resume Control

The suspend resume control logic implements the operations as per the specifications. The SD host request the lower priority or slower transactions to suspend using the DAT lines and restores later aftercompletion of higher priority transactions.

Clock/Resets

This block takes the asynchronous resets as inputs and generates resets synchronized to respective clocks in the design. This block has the clock switching circuit for FIFO control.