It has fixed internal register map. The fixed area will contain information about the card and some mandatory and optional registers. The CIS and CSA will be implemented in internal memory of CPU subsystem. The SDIO registers (CCCR and FBR) can be programmed both by SD host (through SD bus) and CPU (through OCP interface).AHB Master & Slave interface in SDIO IP will allow easy integration in to SOC. Flexible architecture of the core will support wide range of applications – GPS , UWB, WiMAX etc.
Functional Block Description
The registers block consists of fixed internal registers called Common IO Area (CIA). The registers within CIA are provided to enable/disable and control operation of IO functions. There are three types ofregisters supported within CIA .
The 32-bits AHB master interface is used to access the function specific registers and the memory. It supports following transactions
Bus Interface Unit
The SDIO bus interface unit block communicates to the SD host through SD bus. This block contains CRC7 and CRC 16 generator and checker logic for CMD and DAT lines respectively.
CMD/RESP State Machine
It controls the Command receive and Response transmit timing in SDand SPI mode of operations.
Interrupt State Machine
This state machine implements the interrupt timing control as per SDIO 2.0 specifications. It supports optional Interrupt period at the Data Block gap in 4-bit SD mode. It also implements the Read Wait Control logic.
The suspend resume control logic implements the operations as per the specifications. The SD host request the lower priority or slower transactions to suspend using the DAT lines and restores later aftercompletion of higher priority transactions.
This block takes the asynchronous resets as inputs and generates resets synchronized to respective clocks in the design. This block has the clock switching circuit for FIFO control.
- Verilog source / encrypted code of the IP core
- Verilog Test environment and test scripts
- Synthesis constraints and scripts
- Documentation – Design , Verification & Integration guide
- FPGA validation platform (Xilinx / Altera)
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