Aizyc SD/SDIO Device Controller IP is compact low power and scalable IP Core suited for wide range of applications – GPS, UWB, WiMax, Mobile devices or Bluetooth. This device IP core supports SD Physical Layer specifications version 3.01.

Overview

AHB Master & Slave interface in IP will allow easy integration in to SOC. Device IP core supports data transfer rate up to 104 MB/s.  IP core supports SPI, 1-bit SD and 4-bits SD transfer modes. IP has fixed internal register map. The fixed area will contain information about the card and some mandatory and optional registers. The CIS and CSA will be implemented in internal memory of CPU subsystem.  The SD/SDIO registers (CCCR and FBR) can be programmed both by SD host (through SD bus) and CPU (through AHB interface).

The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform

Feature List

• Compliant to

  

  • SDIO specifications version 3.00 Draft 1.01

  • SD Physical Layer Specifications version 3.01

• System Bus Interface – AHB

• Optional Bus Interface - VCI, OCP, AXI, APB

• All SD 3.0 Commands supported - Speed Class, Tuning, Voltage, Block Size Control

• Supports UHS-I modes of operation – DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50

• Supports SPI, 1-bit and 4-bit SD modes

• Maximum Transfer Rate up to 104 MB/s

• Host Clock Rate 0-208 Mhz

• Supports IO52 and IO53 commands for SDIO cards

• Supports CRC7 and CRC16 generation/ checking

• Supports Read Wait Control and Suspend/Resume operations

• Configurable FIFO depths

• Asynchronous Interrupt support

• Supports clock tuning

Functional Block Description

SDIO Registers

The registers block consists of fixed internal registers called Common IO Area (CIA). The registers within CIA are provided to enable/disable and control operation of IOfunctions. There are three types of registers supported within CIA .

AHB DMA

The 32-bits AHB master interface is used to access the function specific registers andthe memory. It supports following transactions on the AHB bus.

• Single

• INCR

Bus Interface Unit

The bus interface unit block communicates to the SD host through SD bus. This block contains CRC7 and CRC 16 generator and checker logic for CMD and DAT lines respectively.

CMD/RESP State Machine

It controls the Command receive and Response transmit timing in SD and SPI mode of operations.

Interrupt State Machine

This state machine implements the interrupt timing control as per SDIO 3.0 specifications. It supports optional Interrupt period at the Data Block gap in 4-bit SD mode. It also implements the Read Wait Control logic by which the SD host can delay Data Read from any function which is using the data lines.

Suspend/Resume Control

The suspend resume control logic implements the operations as per the specifications. The SD host request the lower priority or slower transactions to suspend using the DAT lines and restores later after completion of higher priority transactions.

Clock/Resets

This block takes the asynchronous resets as inputs and generates resets synchronized to respective clocks in the design. This avoids the reset removal violations in the design. This block has the clock switching circuit for FIFO control.