Aizyc USB 2.0 Host Controller IP is compact low power and scalable IP core. USB 2.0 Host Controller, implements an Enhanced Host Controller Interface (EHCI).The IP core is portable to an ASIC or a FPGA. It has been validated on Xilinx platform.
USB 2.0 Host Controller, implements an Enhanced Host Controller Interface (EHCI). The EHCI controller is used for all high-speed communications to high-speed devices connected to the root port. The EHCI specification allows communications to Full-and-Low-speed devices connected to the root port of the USB 2.0 host controller to be provided by companion USB 1.1 host controller.
This IP also has Open Host Controller Interface (OHCI). The Companion Host Controller always manages Full- and Low-speed USB devices connected to the root port. Other interfaces available on request.
- Fully compliant with USB Specification rev 2.0
- Fully complaint to EHCI and OHCI specifications
- Host Controller supports (480 / 12 / 1.5 Mbps)
- Supports Control, Bulk, Isochronous and Interrupt transactions
- VCI interface to external host processor
- VCI interface to external host memory
- Interface to support external UTMI+ PHY
- Root hub supporting two downstream USB ports
Functional Block Description
EHCI and OHCI Controllers
The USB 2.0 Host Controller includes one high-speed mode host controller and one USB 1.1 host controller .The high-speed host controller implements an EHCI interface. It is used for all high-speed communications to high-speed-mode devices connected to the root port of the USB 2.0 host controller.
The EHCI specification allows communications to Full and Low-speed devices connected to the root port of the USB 2.0 host controller to be provided by companion USB 1.1 host controller.
The Companion Host Controller (OHCI) always manages Full and Low-speed USB devices connected to the root port. High-speed devices are always routed to and controlled by the High speed host controller (EHCI).
The 64-Bit DMA Controller handles read/write requests to system memory that are initiated by the Host Controller/Device controller. The major tasks handled by this block areFetching Queue Heads and Queue Element Transfer Descriptors Reading/writing endpoint data from/to system memory Accessing the Periodic Frame List and Periodic Data Structures Writing status back to system memory
The Command Processor block is responsible for front end USB protocol for transmit and receive. The engine receives transaction request, it initiates the transaction depending upon the token fields given by the Host/Device controller. And also takes care of the error detection and CRC generation/checking.
The register block implements the Host control, status, operational registers. These registers control the behavior of the root hub and list processor in the host controller.
32-bit VCI configuration bus interface is provided to write/read internal control/status and operational registers by the host processor.
This interface is provided for external standard ULPI/UTMI+ PHY. This ULPI interface is a wrapper around UTMI+ interface. Any of the two interfaces can be used for external USB PHY