Aizyc USB 3.0 Device Controller IP is compact low power and scalable IP core provided with sample Gigabit bridge application, Evaluation platform and customization support.

Overview
USB3.0 device controller IP core is fully synthesizable core suitable for different process. USB 3.0 Device implements the standard Link Layer, Protocol Layer and Application Layer. It provides an AXI interface to allow integrating end applications and build USB 3.0 Devices. It uses PIPE interface to connect to USB3.0 PHY. USB2.0 core is also included and integrated to allow backward compatibility. The IP core is portable to an ASIC or a FPGA. It has been validated  on Xilinx platform. Along with the IP core, we will provide complete test environment with constraint randomized test cases and our full support during integration.

Features

• Compliant to USB3.0 USB2.0
• PIPE  Interface to connect to PHY
• AXI interface on application end
• Application end list processor for easy integration to SOCs
• Single memory block for OUT transfers
• Option of using single vs. multiple memory blocks for IN transfers
• Supports Control, Bulk, Isochronous and Interrupt endpoint
• 32-bit data paths
• Configurable data width at AXI interface
• Software configurable descriptors
• Number of interfaces and endpoints and their types can be configured at RTL integration
• 250MHz clock at PHY interface and 125 MHz

Functional Block Description

Link layer function
This layer connects PHY through PIPE interface  .It implements LTSSM which performs the link training and link partner detection. It performs link level framing  and deframing.  It also manages the link power management.

Protocol layer function
This layer implements protocol level data transfer mechanisms for all type of end points. It performs burst transfers and handles generation and tracking of header packet fields.

Endpoint FIFO
Every endpoint in the device controller has associated FIFO buffer for data transfer. The buffer size for each endpoint is configurable.

Application layer function
This layer has a command processor that decodes and executes standard as well as vendor specific commands. It implements device state machine that moves based on commands. This layer implements a simple data structure with list processor and DMA so as to allow data transfer to and from memory. It also allows scatter gather to achieve efficient SOC implementation.

FPGA Evaluation Platform

USB3.0 Device Evaluation Board is designed to plug into USB port 3.0 of a desktop or laptop PC. The board has a RJ45 connector for users who wish to connect to 1000Mbps Fast Ethernet LAN in full duplex mode of operation. The board uses a Spartan-6 FPGA and can be connected to any Windows 7 or XP PC for a driver less operation. IPERF and other data blaster applications can be used to test the USB3.0 Device IP performance in real world scenario.